I have a makefile I use to compile a single file. When I need to pass an argument, I use target=targetFile.
The script takes the argument, looks for the file (within the same directory) that has the same value as the argument and compiles it.
I use this for compiling problems from uhunt and uva, which use a single c++ file. So I dont' need multiple makefiles for multiple source files. Single makefile for multiple source files is the reason I made the makefile.
Here's the code I have so far
OBJS = $(target).o CC = g++ CFLAGS = -Wall -g -std=c++11 INCLUDE = -I./$(target) #default command to run all : Main-$(target) clean run #compile and build Main-$(target) : $(OBJS) $(CC) $(CFLAGS) $^ -o $@ %.o : %.cpp $(CC) -c $(CFLAGS) $< #remove object and any other garbage files. clean: rm -rf -d $(target).o *~ *% *# .#* #remove the compiled file clean-all: $(clean) rm Main-$(target) #run the compiled file run: ./Main-$(target)
The command I use to compile is,
Also I don't include the file extension, I have all my source file extensions to be cpp
What I want in the end is:
Just a side note, for using the command clean and clean-all, I use
make target=sourceFile clean
make target=sourceFile clean-all
I'd prefer if I can use:
make sourceFile clean
make sourceFile clean-all